An Asynchronous Transfer Mode (ATM) infrastructure is a popular form of Wide Area Network (WAN) technology. ATM provides a number of benefits such as speed, scalability, and traffic management to carry voice, video, and data using a single uniform protocol. ATM typically uses a T1/E1 link providing a maximum data rate of 1.544 Mbps/2.048 Mbps or a T3/E3 link providing a maximum data rate of 45 Mbps/34 Mbps. The cost of using a T3/E3 link, however, is typically ten times the cost of using a T1/E1 link. Consequently, if a T3/E3 link is used at a fraction of its maximum data rate, the T3/E3 link will not be used cost effectively.
Inverse multiplexing over ATM (“IMA”) offers a solution to such a problem. The ATM Forum Technical Committee provides an “Inverse Multiplexing for ATM (IMA) Specification” ver. 1.1, January 1999, which is herein incorporated by reference, that describes IMA as dividing an aggregate stream of ATM cells across multiple T1/E1 links on a cell-by-cell basis. That is, IMA specifies a transmission method in which ATM cells are fanned across multiple T1/E1 links and then reassembled at the receiving end without loss of the original ATM cell order. By using T1/E1 links, a more cost effective data transmission can be achieved. For example, if an application requires a 5 Mbps transmission rate, 4 T1 links can be used providing bandwidth of approximately 6 Mbps 1 T3 link that provides bandwidth of 45 Mbps. As such, for the T3 link, 39 Mbps of bandwidth is not being used, which is not cost effective.
The constituent T1/E1 links for IMA, however, may have different transmission delays. For example, an ATM cell being transmitted on one link may pass through 2 or more hops (e.g., routers), however; another packet being transmitted on another link may only pass through 1 hop. This can cause differential delays among the T1/E1 links for an IMA group. To compensate for such a delay, an IMA group uses a delay compensation buffer (DCB) for each link. In prior IMA groups, the ATM cells from the faster links of the IMA group are buffered in a DCB and played out with a delay corresponding to the slowest link of the IMA group. Such a delay can cause a number of problems as will be explained in FIGS. 1 through 3.
FIG. 1 illustrates a diagram of a prior art buffering scheme 100 for an IMA group. Referring to FIG. 1, two DCBs 10 and 20 are shown for a two link IMA group. Link 1 for DCB 10 has a differential delay of 2 cells compared with link 2 for DCB 20. The read pointer (“Rptr”) points to the DCB location for reading an ATM cell in the DCBs 10 and 20. Write pointer 1 (“Wptr 1”) for DCB 10 indicates where the next ATM cell for link 1 is to be stored. Write pointer 2 (“Wptr 2”) for DCB 20 indicates where the next ATM cell for link 2 is to be stored. Rptr operates at a per group basis so that cells are read out in the same order. Wptrs 1 and 2 operate at a per link basis and can point to different locations.
The Rptr moves as it reads out the cells (playback). The Wptrs 1 and 2 for each link move at the rate of cell arrival. Each link, however, may transmit packets or cells at a same rate, but may pass through different number of hops. Thus, data may arrive at different times at a receiving end for each link. In prior art DCB schemes, Rptr moves at the rate of the write pointer for the slowest link. In the case the slowest link is later deleted, this scheme can remain the same.
FIG. 2 illustrates a diagram 200 to describe a problem with the prior art buffering scheme for an IMA group. Referring to FIG. 2, two DCBs 10 and 20 are shown for a two link IMA group. If the IMA group allows a maximum delay of 275 milliseconds, to accommodate this amount of delay, the DCBs 10 and 20 should hold at least 1000 ATM cells for the two links. If link 1 for DCB 10 has a differential delay of 240 milliseconds (i.e., link 1 passes through more hops than link 2), the observed delay for the IMA group will be the same as the delay of the slowest link for DCB 10.
A disadvantage of such a scheme is that if link 1 is deleted or removed DCB 20 for link 2 will have 240 milliseconds of buffered ATM cells. That is, if Rptr moves at the rate of the buffer fill rate (i.e., Wptr 1 rate) the buffered ATM cells in DCB 20 never get drained up. Consequently, an unwanted accumulated delay of 240 milliseconds is introduced. Such an unwanted delay is equivalent to the maximum delay of the slowest link that was present in the IMA group.
FIG. 3 illustrates a diagram 300 to describe another problem of the prior art buffering scheme for an IMA group. Referring to FIG. 3, three DCBs 10, 20, and 30 are shown for a three link IMA group. Link 3, which has the fastest buffer fill rate, has a Wptr 3 at the “wrap around point.” The wrap around point indicates that the “outside buffer range” is about to begin. Thus, if Wptr 3 is updated it will wrap around to the beginning of DCB 30. In FIG. 3, the prior buffering scheme would have Rptr rate equal to the buffer fill rate of DCB 10, which is the rate of Wptr 1.
A disadvantage of such a buffering scheme is that if a slow link (e.g., link 1) is waiting to be filled and a fast link (e.g., link 3) is rapidly being filled Wptr 3 will wrap around and cells in DCB 30 that has not been read will be lost. That is, such a prior art buffering scheme would overwrite the unread cells in DCB 30 after a wrap around. In such a case, link 3 could never be added to the IMA group.
Another disadvantage with such a scheme is that if another link is added that is faster than link 2, e.g., by 60 milliseconds, the overall delay of the group will be 300 milliseconds. Consequently, the added link will exceed the allowed maximum differential delay of 270 milliseconds. In such a case, even though the differential delay between two constituent links is 60 milliseconds, the new link cannot be added because it will violate the maximum delay allowable.